When information is transmitted over a communications link between a receiver and a transmitter, the bits that describe the information being transmitted can be corrupted. In other words, the receiver may determine that a received bit that is supposed to be a binary 1 is a binary 0, and vice versa. Corruption of bits in a data stream may be caused by a variety of factors or components in the communications link. For example, in an optical fiber network, optical energy is transmitted in the form of optical pulses that have particular levels that correspond to binary 1 s and 0 s. If the level of the optical energy is too low, the receiver can have difficulty determining whether a pulse corresponds to a binary 1 or a binary 0. Repeaters, or amplifiers, normally are disposed at particular locations along the communications link that amplify the optical signals so that they are at the proper levels to enable the receiver to determine whether it has received a binary 1 or a binary 0. Typically, the optical signals are converted into electrical signals at the repeaters. The electrical signals are then amplified and converted into optical signals, which are then modulated back onto the optical fiber. Similarly, at the receiver, the optical signals typically are converted back into electrical signals, which the receiver compares to a threshold value to determine whether it has received a binary 1 or a binary 0.
Because it is possible for the bits to be corrupted, techniques have been developed and implemented that provide error correction. In other words, if a bit received by the receiver is erroneously determined to be a binary 1 when it was meant to be a binary 0 when it was transmitted, and vice versa, receivers utilize various techniques to determine whether a bit value has been incorrectly identified and to correct the bit value. One known technique used for such purposes is generally referred to as the “Automatic Request To Transmit” (ARM) technique. In accordance with this technique, when the receiver detects a bit error, it sends a signal to the transmitter that tells the transmitter to retransmit the block of data that contained the error. The receiver processes the retransmitted data block and detects bit errors. The data block may need to be retransmitted several times before the receiver determines that the data is without error. Of course, retransmitting data utilizes bandwidth and generally slows down the overall throughput of the communications system.
A technique known as Forward Error Correction (FEC) is commonly used in the communications industry to reduce errors in data being transmitted over a communications link without requiring retransmission of data. FEC not only detects bit errors, but corrects detected bit errors. One of the primary advantages of FEC over ARM is that no retransmission of data is required with FEC. This is because FEC techniques introduce redundancy in the data bits that enables the receiver of a communications system to detect errors in data being transmitted and to correct the detected errors. The redundancy generally is introduced by utilizing data bits from the data stream to encode the data stream. The receiver has a decoder that has intelligence with regard to the encoding scheme used by the transmitter, which enables the receiver to decode the data and detect and correct errors without the need for retransmission. Another advantage of FEC is that, because it does not require retransmission of data, simplex links can be used, which is desirable in certain situations, such as when the receivers are receive-only terminals.
Generally, FEC techniques and systems fall into two broad categories, namely, block coding and convolution coding. Various block coding and convolution coding techniques are currently in use in the communications industry. In the past, the use of block codes has generally been limited to use in communications systems that have relatively low data rates for various reasons, such as the aforementioned adverse effects on overall coding gain (signal-to-noise ratio, Eb/No), which is expressed in decibels (dB), for short data bursts and the reduced overall throughput that can result from the synchronization requirement. Convolution coding has generally been the preferred FEC technique for high data rate implementations. However, convolution coding results in higher output bit error rates (BER) than the output (BERs) that can be achieved using block coding. Some customers want FEC systems with very low BERs (e.g., 10−15), which generally cannot be achieved using convolution coding, but which can be achieved using block coding, such as Bose-Chaudhuri-Hocquenghem (BCH) block coding, for example.
However, FEC systems that implement block coding have, to date, required a large number of encoders and decoders to process the relatively large amount of data in a data block. For example, one known FEC system utilizes 16 parallel encoders to process a 128-bit data block (i.e., each encoder processing 8 bits of the code) in parallel. In order to implement 16 parallel encoders in this known FEC system, a very large number of logic gates are required, which is undesirable for at least two reasons, namely, (1) the design increases the amount of “real estate” needed on an integrated circuit (IC) to implement the encoders, and (2) the large number of gates consume a large amount of power. Furthermore, this known FEC system only achieved a data rate of 2.5 gigabits per second (Gb/s), which is too slow for certain communications systems, such as current 10 Gb/s and 40 Gb/s optical communications systems. When designing integrated circuits (ICs) with FEC systems that utilize long block codes, such as long BCH codes, for example, it is difficult to determine the maximum power dissipation of the IC. Long BCH decoders have a power dissipation that increases significantly with incoming bit error rate (BER) due to the extensive use of Exclusive-OR (XOR) trees that have a high switching factor.
It would be desirable when designing such an IC to be able to estimate the power dissipation with a high degree of accuracy in order to design the power distribution network of the IC properly. Otherwise, costly re-spins of the IC may be necessary due to excessive voltage drop from the IC package pins to the internal die of the IC. Accordingly, a need exists for a method and apparatus for generating bit errors that can be used to test the FEC system in order to estimate the power dissipations of the system to ensure that the power distribution network of the system is designed to meet the necessary power requirements.